View ICS843251I-12_1253018.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843251I-12 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
FEATURES
* One Differential LVPECL output * Crystal oscillator interface, 18pF parallel resonant crystal (23.2MHz - 30MHz) * Output frequency range: 290MHz - 750MHz * VCO range: 580MHz - 750MHz * RMS phase jitter @ 312.5MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.36ps (typical) * 3.3V or 2.5V operating supply * -40C to 85C ambient operating temperature * Available in both standard and lead-free RoHS-compliant packages
GENERAL DESCRIPTION
The ICS843251I-12 is a 10Gb Ethernet Clock Generator and a member of the HiPerClocksTM HiPerClockSTM family of high performance devices from ICS. The ICS843251I-12 uses an 18pF parallel resonant crystal over the range of 23.2MHz - 30MHz. For Ethernet applications, a 25MHz crystal is used. The device has excellent <1ps phase jitter performance, over the 1.875MHz - 20MHz integration range. The ICS843251I-12 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space.
IC S
COMMON CONFIGURATION TABLE
Inputs Crystal Frequency (MHz) 25 25 FREQ_SEL 0 1 M 25 25 N 1 2 Multiplication Value M/N 25 12.5 Output Frequency (MHz) 625 312.5
BLOCK DIAGRAM
FREQ_SEL
Pullup
PIN ASSIGNMENT
FREQ_SEL N 0 /1 1 /2
VCCA VEE XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VCC Q nQ FREQ_SEL
XTAL_IN
OSC
XTAL_OUT
Phase Detector
VCO
580MHz - 750MHz
Q nQ
ICS843251I-12
8-Lead TSSOP 4.4mm x 3.0mm x 0.925mm package body G Package Top View
M = /25 (fixed)
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843251BGI-12 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
1
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843251I-12 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3, 4 5 6, 7 8 Name VCCA VEE XTAL_OUT, XTAL_IN FREQ_SEL nQ, Q VCC Power Power Input Input Output Power Pullup Type Description Analog supply pin. Negative supply pin. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Frequency select pin. LVCMOS/LVTTL interface levels. Differential clock outputs. LVPECL interface levels. Core supply pin.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP Parameter Input Capacitance Input Pullup Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF k
843251BGI-12
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 10, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843251I-12 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG 4.6V -0.5V to VCC + 0.5V 50mA 100mA 101.7C/W (0 mps) -65C to 150C
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = -40C TO 85C
Symbol VCC VCCA IEE Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 TBD Maximum 3.465 3.465 Units V V mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 2.5V5%, TA = -40C TO 85C
Symbol VCC VCCA IEE Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Test Conditions Minimum 2.375 2.375 Typical 2.5 2.5 TBD Maximum 2.625 2.625 Units V V mA
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Test Conditions VCC = 3.3V VCC = 2.5V VCC = 3.3V VCC = 2.5V VCC = VIN = 3.465V or 2.625V VCC = 3.465V or 2.625V, VIN = 0V -150 Minimum 2 1.7 -0.3 -0.3 Typical Maximum VCC + 0.3 VCC + 0.3 0.8 0.7 5 Units V V V V A A
843251BGI-12
www.icst.com/products/hiperclocks.html
3
REV. A JANUARY 10, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843251I-12 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC - 1.7 1.0 Units V V V
TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions
NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level 23.2 Test Conditions Minimum Typical Fundamental 30 TBD 7 TBD MHz pF mW Maximum Units
TABLE 5A. AC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = -40C TO 85C
Symbol fOUT t jit(O) t R / tF Parameter Output Frequency RMS Phase Jitter ( Random); NOTE 1 Output Rise/Fall Time Test Conditions F_SEL = 1 F_SEL = 0 312.5MHz @ Integration Range: 1.875MHz - 20MHz 20% to 80% Minimum Typical 312.5 625 0.36 325 50 Maximum Units MHz MHz ps ps %
odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plots following this section.
TABLE 5B. AC CHARACTERISTICS, VCC = VCCA = 2.5V5%, TA = -40C TO 85C
Symbol fOUT t jit(O) tR / tF Parameter Output Frequency RMS Phase Jitter ( Random); NOTE 1 Output Rise/Fall Time Test Conditions F_SEL = 1 F_SEL = 0 312.5MHz @ Integration Range: 1.875MHz - 20MHz 20% to 80% Minimum Typical 312.5 625 0.38 325 50 Maximum Units MHz MHz ps ps %
odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plots following this section.
843251BGI-12
www.icst.com/products/hiperclocks.html
4
REV. A JANUARY 10, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843251I-12 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
AT
TYPICAL PHASE NOISE
312.5MHZ (3.3V)
0 -10 -20 -30 -40 -50 -60 -70 -80
10GigE Filter 312.5MHz
RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.36ps (typical)
NOISE POWER dBc Hz
-90
Raw Phase Noise Data
-100 -110 -120 -130 -140 -150
1k 10k
-160 -170 -180 -190 100
Phase Noise Result by adding 10GigE Filter to raw data
100k
1M
10M
100M
OFFSET FREQUENCY
843251BGI-12
www.icst.com/products/hiperclocks.html
5
REV. A JANUARY 10, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843251I-12 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V 2V
VCC, VCCA
Qx
SCOPE
VCC, VCCA
Qx
SCOPE
LVPECL
nQx
LVPECL
nQx
VEE
VEE
-1.3V 0.165V
-0.5V 0.125V
LVPECL 3.3V OUTPUT LOAD AC TEST CIRCUIT
LVPECL 2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Noise Power
nQ
Phase Noise Mask
Q
t PW
t
PERIOD
f1
Offset Frequency
f2
odc =
t PW t PERIOD
x 100%
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
OUTPUT RISE/FALL TIME
843251BGI-12
www.icst.com/products/hiperclocks.html
6
REV. A JANUARY 10, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843251I-12 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843251I-12 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin. The 10 resistor can also be replaced by a ferrite bead.
3.3V or 2.5V VCC .01F VCC .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843251I-12 has been characterized with 18pF parallel resonant crystals. The capacitor values (TBD), C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_IN C1 X1 Crystal XTAL_OUT C2
Figure 2. CRYSTAL INPUt INTERFACE
843251BGI-12
www.icst.com/products/hiperclocks.html
7
REV. A JANUARY 10, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843251I-12 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
TERMINATION
FOR
3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are
Zo = 50
3.3V 125 125
FOUT
FIN
Zo = 50
Zo = 50
FOUT
50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FIN
Zo = 50 84 84
RTT =
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
843251BGI-12
www.icst.com/products/hiperclocks.html
8
REV. A JANUARY 10, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843251I-12 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C.
TERMINATION
FOR
2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
843251BGI-12
www.icst.com/products/hiperclocks.html
9
REV. A JANUARY 10, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843251I-12 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
8 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2.5
89.8C/W
TRANSISTOR COUNT
The transistor count for ICS843251I-12 is: 2377
843251BGI-12
www.icst.com/products/hiperclocks.html
10
REV. A JANUARY 10, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843251I-12 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
PACKAGE OUTLINE - G SUFFIX
FOR
8 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 2.90 6.40 BASIC 4.50 Millimeters Minimum 8 1.20 0.15 1.05 0.30 0.20 3.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
843251BGI-12
www.icst.com/products/hiperclocks.html
11
REV. A JANUARY 10, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843251I-12 FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
Package Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS843251BGI-12 ICS843251BGI-12T ICS843251BGI-12LF ICS843251BGI-12FT Marking TBD TBD BI12L BI12L 8 Lead TSSOP 8 Lead TSSOP 8 Lead "Lead-Free" TSSOP 8 Lead "Lead-Free" TSSOP
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843251BGI-12
www.icst.com/products/hiperclocks.html
12
REV. A JANUARY 10, 2006

▲Up To Search▲

Price & Availability of ICS843251I-12

	To Download ICS843251I-12 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .